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POWER8 is a family of superscalar symmetric multiprocessors based on the Power Architecture, and introduced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for such availability of IBM's highest-end processors.〔(You won't find this in your phone: A 4GHz 12-core Power8 for badass boxes )〕〔(POWER8 Processor User’s Manual for the Single-Chip Module )〕 Systems based on POWER8 became available from IBM in June 2014.〔(IBM POWER8 - Announce / Availability Plans )〕 According to Ken King at IBM, systems and POWER8 processor designs made by other OpenPOWER members will be available in early 2015, but Tyan seems to be ready to ship earlier than that, in October 2014.〔(【引用サイトリンク】title=Tyan Ships First Non-IBM Power8 Server )〕 == Design == POWER8 is designed to be a massively multithreaded chip, with each of its cores capable of handling eight hardware threads simultaneously, for a total of 96 threads executed simultaneously on a 12-core chip. The processor makes use of very large amounts of on- and off-chip eDRAM caches, and on-chip memory controllers enable very high bandwidth to memory and system I/O. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the POWER7.〔(【引用サイトリンク】title=IBM's Watson could get even smarter with Power8 chip )〕 Where previous POWER processors use the GX++ bus for external communication, POWER8 removes this from the design and replaces it with the CAPI port (Coherent Accelerator Processor Interface) that is layered on top of PCI Express 3.0. The CAPI port is used to connect auxiliary specialized processors such as GPUs, ASICs and FPGAs.〔(【引用サイトリンク】title=IBM Power8 Processor Detailed - Features 22nm Design With 12 Cores, 96 MB eDRAM L3 Cache and 4 GHz Clock Speed )〕 Units attached to the CAPI bus can use the same memory address space as the CPU, thereby reducing the computing path length. At the 2013 ACM/IEEE Supercomputing Conference, IBM and Nvidia announced an engineering partnership to closely couple POWER8 with Nvidia GPUs in future HPC systems, with the first of them announced as the Power Systems S824L. POWER8 also contains a so-called ''on-chip controller'' (OCC), which is a power and thermal management microcontroller based on a PowerPC 405 processor. It has two general-purpose offload engines (GPEs) and 512 KB of embedded static RAM (SRAM), together with the possibility to access the main memory directly, while running an open-source firmware. OCC manages POWER8's operating frequency, voltage, memory bandwidth, and thermal control for both the processor and memory; it can regulate voltages through 1,764 integrated voltage regulators (IVRs) on the fly. Also, the OCC can be programmed to overclock the POWER8 processor, or to lower its power consumption by reducing the operating frequency (which is similar to the configurable TDP found in some of the Intel and AMD processors).〔(【引用サイトリンク】title=Semiconductor Engineering .:. The Good Kind Of Regulation )〕 POWER8 comes in 4-, 6-, 8-, 10- and 12-core variants;〔〔(【引用サイトリンク】title=IBM Power System S814 )〕 each version is fabricated in a 22 nm silicon on insulator (SOI) process using 15 metal layers. The 12-core version consists of 4.2 billion transistors〔(【引用サイトリンク】title=POWER8: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth )〕 and is 650 mm2 large while the 6-core version is only 362 mm2 large.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「POWER8」の詳細全文を読む スポンサード リンク
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